1. Field of the Invention
The present invention relates to a semiconductor memory device, a method of manufacturing the same and a method of using the same. More particularly, the present invention relates to a semiconductor memory device including a memory device which can be written/read at any time (i.e., an SRAM: Static Random Access Memory), a method of manufacturing the same and a method of using the same.
2. Description of the Background Art
Conventionally, an SRAM is known as one type of semiconductor memory device. When compared to a DRAM (Dynamic Random Access Memory), this SRAM has an advantage that it does not require a refresh operation and its state of storage is stable.
FIG. 42 is an equivalent circuit diagram of one memory cell in a conventional SRAM. Referring to FIG. 42, this memory cell employs a p type MOS (Metal Oxide Semiconductor) transistor as the load and is formed of six transistors. More specifically, it is formed of a pair of access transistors Q3, Q4 (which are n type MOS transistors), a pair of driver transistors Q1, Q2 (which are n type MOS transistors) and a pair of load transistors Q5, Q6 forming a flip flop circuit.
Each of the paired load transistors Q5 and Q6 has its one source/drain region connected to a Vcc power supply, and their other source/drain regions are connected to storage nodes N1 and N2, respectively. Each of driver transistors Q1 and Q2 has its one source/drain region connected to GND, and their other source/drain regions are connected to storage nodes N1 and N2, respectively. Driver transistor Q1 and load transistor Q5 have each of their gates connected to storage node N2, and driver transistor Q2 and load transistor Q6 have each of their gates connected to storage node N1, respectively.
In addition, a pair of access transistors Q3 and Q4 each have one of their source/drain regions connected to storage nodes N1 and N2, respectively. The other source/drain regions of access transistors Q3 and Q4 are each connected to bit lines BL and /BL, respectively. Also, the gate electrodes of access transistors Q3 and Q4 are in connection with a word line WL.
In the memory cell of this SRAM, thin film transistors (TFT) are generally employed as the pair of load transistors Q5 and Q6.
FIGS. 43 and 44 are schematic cross sectional views showing load transistors formed of thin film transistors of bottom gate and top gate types. Referring to FIG. 43, load transistor Q5 (or Q6) has a gate electrode layer 301, and a pair of source/drain regions 303a, 303c formed at a semiconductor layer to define a channel region 303b. Gate electrode layer 301 is formed to be opposite to this channel region 303b with a gate insulating film therebetween. This load transistor Q5 (or Q6) is a so-called bottom gate type thin film transistor, and thus gate electrode 301 is arranged below channel region 303b.
Referring to FIG. 44, this load transistor Q5 (or Q6) is a so-called top gate type thin film transistor, and thus a gate electrode layer 301 is arranged above a channel region 303b.
In the structures of the conventional thin film transistors shown in FIGS. 43 and 44, there has been a problem that the stability of the operation of the memory cell is degraded when reduction in the voltage has caused decrease the power supply voltage. The following is a detailed description of this problem.
FIG. 45 is a graph showing a characteristics of a typical p channel TFT concerning drain current I.sub.D and gate voltage V.sub.G. Referring to FIG. 45, there are two points required for this TFT characteristic, that is, (1) to reduce the current which flows when TFT is turned OFF (i.e., OFF current), and (2) to increase the current which flows when TFT is turned ON (i.e., ON current).
The above (1) is required so as to reduce the power consumption during standby, since the power consumed during standby is determined by OFF current.times.the number of cells in one TFT.
The above (2) is required so as to improve the stability of the operation of the memory cell, since when ON current is increased, the potential of the storage node connected to one source/drain region of the TFT which is turned ON becomes more closer to Vcc and the difference between the High potential of that storage node and the Low potential of the other storage node is made distinct.
To what extent the ON current of the TFT is required will be described in the following, although it is certain that the stability of operation of the memory cell is increased in proportion to the amount of ON current.
FIG. 46 is a diagram of a portion of the circuit of the SRAM, in which the voltage at the portion of the storage node storing High immediately after reading or writing is shown. Referring to FIG. 46, the potential at storage node N1 immediately after reading/writing is High, but it has not fully reached Vcc and is expressed as Vcc-Vth.sub.A. Here, Vcc is the power supply voltage, and Vth.sub.A is the threshold voltage of an access transistor. Owing to the amount of decrease in the potential of storage node N1 due to Vth.sub.A, the operation of the memory cell immediately after reading/writing is unstable. TFT Q5 serves to charge storage node N1 to make up for this amount of decrease due to Vth.sub.A.
Here, when Vth.sub.A is 1 V and the capacitance of storage node N1 is 5 fF, the ON current of TFT required to charge this storage node N1 within a time period of 5 nsec would be expressed as follows. ##EQU1##
Since the channel region is of a polycrystalline silicon in a TFT, the S-factor in the I.sub.D -V.sub.G characteristic shown in FIG. 45 is increased (that is, the gradient is made small). Here, S-factor represents a gate voltage V.sub.G required for I.sub.D to increase by one order of magnitude.
Accordingly, with reference to FIG. 45, when power supply voltage is reduced from -Vcc to -Vcc' owing to reduction of the voltage, this ON current of TFT is also reduced from I.sub.D1 to I.sub.D2. Thus, in the structure of TFT employed in the conventional SRAM, it was difficult to implement a large ON current while maintaining a small OFF current.
Moreover, since the channel region is of polycrystalline silicon, the characteristic of TFT is varied depending on whether there is a grain boundary in this channel region or not. Limitation on the above-described ON current (the value-required being 1 .mu.A) must hold even when there is a variation in the characteristic of TFT. Accordingly, when this variation in the characteristics of TFT is taken into consideration, it was still more difficult to implement a large ON current while maintaining a small OFF current.